Index -- All Volumes

Symbols

!GND node 3-17
$ comment delimiter 3-9
$installdir installation directory 3-50
* comment delimiter 3-9

A

A model parameter 14-19
A2D
   function 5-50 , 26-4
   model parameter 5-50
   output model parameters 5-54
    See also mixed mode
.a2d file 3-55 , 3-57 , 5-50
AB model parameter 15-35
ABS element parameter 26-12 , 26-18 , 26-23 , 26-28
abs(x) function 7-9
ABSH option 9-20 , 9-38 , 10-36 , 11-15 , 12-7
ABSI option 9-20 , 10-35 , 10-37
   KCLTEST setting 9-21 , 10-26
ABSMOS option 9-20 , 10-35 , 10-37
   KCLTEST setting 9-21 , 10-26
absolute
   power function 7-9
   value function 7-9
   value parameter 26-12 , 26-18 , 26-23 , 26-28
ABSTOL option 9-21 , 10-22
ABSV option 9-38 , 10-35 , 11-15
ABSVAR option 9-43 , 9-46 , 11-15 , 11-18 , 11-27
ABSVDC option 9-21 , 10-38
AC
   analysis 8-3
      circuit and pole/zero models 29-47
      distortion 12-9
      MOSFETs 20-24
      noise 12-11
      RC network 2-2
   control options 12-7
   magnitude calculation 9-5 , 9-39 , 12-7
   network analysis 12-14
   optimization 12-4
   output
      calculation method 9-5 , 9-39 , 12-7
      variables analysis 8-29
   phase calculation 9-5 , 9-39 , 12-7
   resistance 12-3
      parameter 26-74
      transmission lines C-19
   small signal analysis 9-38
      flow 12-2
   sources 5-5
.AC statement 13-5 , 13-39
   external data 3-22
   keywords 12-5
   parameters 12-5
   uses 12-4
.ac# file 3-55 , 3-57
accessing customer support vi
ACCT option 8-16 , 9-5
ACCURACY
   element parameter 29-10
accuracy
   control options 10-36
   simulation time 10-35
   tolerance 10-34
ACCURATE option 9-38 , 11-16 , 11-27
ACM 17-3
   model parameter 11-27 , 17-3 , 20-27
   MOS diode 20-31 , 20-34 , 20-37 , 20-41
   parameter 20-9 , 20-26
      equations 17-22
acos(x) function 7-9
ACOUT option 8-30 - 8-32 , 9-5 , 9-39 , 12-7
adder
   circuit 31-3
   demo 31-3
   NAND gate binary 31-4
   subcircuit 31-3
admittance
   AC input 8-34
   AC output 8-34
   Y parameters 8-29
AF model parameter 12-13
AGAUSS keyword 13-16
ALFA, .FFT parameter 28-8
algebraic
   equations, example 24-11
   expressions 7-8
   models 11-27
algorithms
   Damped Pseudo Transient algorithm 10-48
   DVDT 9-43 , 9-48 , 11-13 , 11-15 , 11-33 , 11-34
   GEAR 9-48 , 11-13 , 11-29
   integration 11-29
   iteration count 11-33
   Levenberg-Marquardt 13-53
   local
      truncation error 9-41 , 9-48 , 11-13 , 11-19 , 11-33 , 11-34
         timestep 9-40 , 11-18
   Muller 27-3
   pivoting 9-24 , 9-26 , 10-27
   timestep control 9-44 , 11-12 , 11-32 , 11-33 , 11-35
   transient analysis timestep 9-48 , 11-13
   TRAP 9-48 , 11-13
   trapezoidal integration 9-49 , 11-14 , 11-29
ALL keyword 10-6 , 10-13
ALPHA model parameter 14-19
.ALTER
   blocks 3-41 - 3-42
   statement 3-40
      failure 8-18
      limit 8-18
      multiple .ALTER's 3-42
      PCI modeling 25-44
      with .DEL LIB 3-42
alternate saturation
   model parameters
      LEVELs 6, 7 21-57
AM
   behavioral 26-62
   modulation frequency 28-13
   source function 5-22 , 5-22
AMD models 20-5 , 20-6
AMI gate capacitance model 20-94
AMP model parameter 26-66
amplifiers, pole/zero analysis 27-12 , 27-14
analog
   behavioral
      elements 26-53
      modeling 26-4
   circuit simulation of a digital system 25-4
   device models D-5
Analog Artist interface 9-11
   output data format 9-12
    See also Artist
Analysis
   FAQ A-2
analysis
   AC 8-3
   accuracy 10-34 - 10-35
   circuit model 29-47
   data driven 13-2 , 13-3 , 24-9
   DC 8-3
   distortion 12-9
   element template 8-4
   FFT 11-44
      example
         AM modulation 28-13
         modulator/demodulator 28-16
         test circuit 28-24
      windows 28-3
   Fourier 11-37
   initialization 10-3
   inverter 2-7
   .MEASURE statement 8-4
   Monte Carlo 13-3 , 13-14 , 13-14 - 13-34 , 18-52
   MOSFETs
      AC 20-24
         noise 20-25
      transient 20-23
   network 12-14
   noise 16-58
   optimization 13-39
   parametric 8-4
   pole/zero 10-21 , 27-1
      example
         active low-pass filter 27-15
         CMOS differential amplifier 27-12
         high-pass Butterworth filter 27-10
         Kerwin's circuit 27-8
         low-pass filter 27-5
         simple amplifier 27-14
      model 29-47
      overview 27-2
      using Muller method 27-3
   pulse width 30-16
   RC network
      AC 2-2
      transient 2-5
   setup time 30-10
   spectrum 28-1
   statistical 13-8 - 13-34
   Taguchi 13-2
   temperature 13-2 , 13-5
   timing 30-1
   transfer function (.TF) 26-46
   transient 8-3 , 11-3
   worst case 13-2 , 13-8 - 13-34
   yield 13-2
arccos(x) function 7-9
arcsin(x) function 7-9
arctan(x) function 7-9
area
   calculation method See ACM
   JFETs and MESFETs
      equations 17-22 - 17-24
      units 17-22 , 17-24
AREA capacitor parameter 15-6
arithmetic operators 7-9
ARTIST option 9-11 , 9-12
ASCII output data 9-11 , 9-12
ASIC
   device libraries 3-51
   vendor libraries 3-51
asin(x) function 7-9
ASPEC
   AMI model 20-5
   compatibility 9-13 , 20-3 , 20-37 , 21-86
   option 9-13 , 20-11
asterisk comment delimiter 3-9
asymptotic waveform evaluation 29-2
   transfer function 29-35
AT keyword 8-42
AT1 model parameter C-36
atan(x) function 7-9
ATEM characterization system 3-50
ATLEN model parameter C-36
AUNIF keyword 13-16
AURORA user's group vi
autoconvergence 10-42
   algorithm 9-31 , 10-39
   disabling 9-31 , 10-39
automatic model selection
   failure D-3
   multisweep or .TEMP effect D-4
    See also model selection
AUTOSTOP option 9-41 , 11-20 , 11-25 , 24-9 , 26-74
AV model parameter 26-67
AV1K model parameter 26-67
AvanLink
   Cadence products B-2
   DA
      design flow B-10
      environment B-9
      Netlister B-12
      schematic B-10
      simulation B-12
   design flow B-4
   environment B-3
   library operations B-5
   Mentor Graphics products B-8
   netlist B-6
   schematic B-5
   simulation B-7
Avant! web site vi
AvanWaves waveform display B-7 , B-12
AVD model parameter 26-67
average deviation 13-3
average value, measuring 8-46
AVG keyword 8-47
AWE See asymptotic waveform evaluation

B

B# node name in CSOS 3-19
backslash continuation character 3-3 , 7-8
   double 7-8
   in input files 3-3
BADCHR option 3-3 , 9-15
bandwidth C-79
BART FFT analysis keyword 28-8
Bartlett FFT analysis window 28-4 , 28-5 , 28-26
base
   charge equations 16-32
   collector capacitance 16-36
   resistance equations 16-32
base-collector junction 16-5
base-emitter
   capacitance equations 16-34
   junction 16-5
basic model parameters
   BJTs 16-6
   JFETs TOM model 17-46
   MOSFETs
      LEVEL 1 21-2
      LEVEL 13 21-107
      LEVEL 2 21-7 - 21-8
      LEVEL 27 21-138
      LEVEL 28 21-152
      LEVEL 3 21-19
      LEVEL 38 21-164
      LEVEL 39 21-179
      LEVEL 40 21-207
      LEVEL 47 22-2
      LEVEL 49, 53 22-34
      LEVEL 5 21-34
      LEVEL 50 22-56
      LEVEL 57 22-117
      LEVEL 58 22-134
      LEVEL 8 21-89
      LEVELs 6, 7 21-52 - 21-54
behavioral
   741 op-amp 26-76
   amplitude modulator 26-62
   AND and NAND gates 26-31
   BJTs
      modeling 26-92
      phase detector model 26-97
   CMOS inverter 26-46
   comparator 26-79
   components 26-40
   current source 5-34 , 26-16
   data sampler 26-63
   device models D-8
   differentiator 26-55
   D-Latch 26-32
   double-edge triggered flip-flop 26-36
   elements
      analog 26-53
      using 26-3
   flip-flop 26-36
   gates 26-31
   integrator 26-53
   LC oscillator 26-83
   look-up tables 26-40
   n-channel MOSFETs 26-34 , 26-42
   p-channel MOSFETs 26-34
   phase detector model 26-88
   phased locked loop 26-88
   ring oscillator 26-50
   silicon controlled rectifier 26-59
   transformer 26-57
   triode vacuum tube 26-60
   tunnel diode 26-58
   VCO model 26-81
   voltage source 5-29 , 26-11
   VVCAP model 26-84
Berkeley
   BSIM3-SOI model 22-114
   junction model 22-24
   NonQuasi-Static (NQS) model 22-23
beta degradation 16-6
BETA keyword 12-14
Biaschk 11-9
BiCMOS
   circuits 16-2
   devices 16-2
bidirectional circuits, wire RC model 14-2
binary
   output data 9-12
   search 30-6 - 30-12
Bipolar Junction Transistors. See BJTs
bisection
   data, printing 9-8
   error tolerance 30-8
   function 30-1
      syntax 30-7
   methodology 30-5
   overview 30-2
   pass-fail method 30-5
   requirements 30-6
   violation analysis 30-4
BISECTION model parameter 30-7
BJTs
   base
      charge equations 16-32
      push-out effects 16-50
      width modulation model parameters 16-9
   base-collector
      depletion capacitance equations 16-37
      diffusion capacitance equations 16-36
   base-emitter
      depletion capacitance equations 16-35
      diffusion capacitance equations 16-34
   beta
      degradation 16-6
      temperature equations 16-42 - 16-46
   capacitance temperature equations 16-46
   conductance 16-21 , 16-22
   current
      equations 16-29
      flow 8-24
   DC 16-6
      models
         equations 16-29
         parameters 16-6
   element template listings 8-59
   elements, names 4-15
   energy gap temperature equations 16-42
   equations 16-28
   equivalent circuits 16-20 , 16-21
   excess phase equation 16-39
   EXPLI 9-19
   geometric 16-6
   high current Beta degradation parameters 16-10
   junction capacitance
      equations 16-37
      model parameters 16-11
   junction capacitor 16-6
   LEVEL 2
      model parameters 16-13
      temperature equations 16-49
   LEVEL 4, model parameters 16-63 - 16-66
   LEVEL 8 HiCUM
      parameters 16-95
   LEVEL 8, HiCUM 16-93
   low current Beta degradation parameters 16-9
   .MODEL statement 16-3
   models
      constants (table) 16-27
      convergence 16-3
      names 16-4
      parameters 16-6 , 16-63 - 16-66
      quasi-saturation 16-50
      statement 16-4
      transistor D-9
      variables (table) 16-25
   noise 16-6
      equations 16-40
      model parameters 16-13
      summary printout 16-41
   npn identifier 16-4
   parasitic capacitance 16-6
   parasitics
      capacitance model parameters 16-12
      resistance model parameters 16-10
      resistor temperature equations 16-49
   pnp identifier 16-4
   power dissipation 8-26
   quasi-saturation model 16-50
   resistor 16-6
   saturation temperature equations 16-42 - 16-46
   scaling 16-20
   S-parameters, optimization 13-60
   subcircuits, scaled 16-55
   substrate
      capacitance equations 16-39
      current equation 16-31
   temperature
      capacitance equations 16-46
      compensation equations 16-42
      effect parameters 16-14
      parasitic resistor 16-49
      saturation equations 16-44
   transit time 16-6
      model parameters 16-12
   variable base resistance equations 16-32
BKPSIZ option 9-41 , 11-20
BLACK FFT analysis keyword 28-8
Blackman FFT analysis window 28-4 , 28-27
Blackman-Harris FFT analysis window 28-4 , 28-28
bond wire example 31-12
branch current
   error 9-20 , 9-21 , 10-22 , 10-37
   output 8-22
branch matrix C-33
breakpoint table
   reducing size 11-36
   size 9-41 , 11-20
BRIEF
   keyword 10-6
   option 9-2 , 9-6 , 9-7 , 9-8 , 9-9
Broyden update data, printing 9-8
BSIM model 21-101
   equations 21-112
   LEVEL 13 3-31 , 20-5
      example 21-121
   VERSION parameter effects 21-111
BSIM2 LEVEL 39 model 3-31
BSIM2 model 21-179
   equations 21-186
   LEVEL 39 20-6
   VERSION parameter effects 21-193
BSIM3 model
   equations 22-10
      Leff/Weff 22-9
   LEVEL 47 20-6
   SOI FD 22-147
BSIM3 SOI FD
   parameters 22-149
   template output 22-157
BSIM3 Version 2 MOS model 22-2
BSIM3v3 model
   MOS 22-19
   with Star-Hspice 22-32
BSIM4 model 22-66
   parameters 22-67
buffer 4-27 , 19-6
   differential pins 19-36
   ECL
      input 19-19
      input/output 19-23
      output 19-20
      tristate 19-21
   IBIS 19-1
   input 19-6 , 19-7
      example 19-42
   input/output 19-16
      open drain 19-18
      open sink 19-18
      open source 19-19
      syntax 19-15
   open
      drain 19-18
      sink 19-18
      source 19-18
   output 19-8 , 19-9
      example 19-42
   scaling strength 19-38
   tristate 19-11 , 19-12
bulk
   charge effect 20-3
   semiconductor devices 17-2
   transconductance, MOSFETs 20-23
BULK wire model parameters 14-4
Burr-Brown devices D-9
bus notation 5-68
BUS wire RC model 14-2
Butterworth filter pole/zero analysis 27-10
BV diode model parameter 15-4
BW model parameter 26-69
BYPASS option 9-42 , 11-11 , 20-11 , 20-13
BYTOL option 9-42 , 11-16

C

C2 model parameter 26-68
Cadence
   Analog Artist
       See Artist, Analog Artist
      with AvanLink B-2
   Composer, with AvanLink B-2
   Opus 9-11
   WSF format 9-11
capacitance
   base collector 16-36
   CAPOP model selector 20-7
   charge tolerance, setting 9-39 , 11-16
   circuit C-33
   control options 20-68
   CSHUNT node-to-ground 9-39 , 11-12
   DCAP 15-5 , 16-2
   DCCAP 15-5 , 16-2
   diode, Fowler-Nordheim 15-49
   distribution for wire RC model 14-2
   effective 14-10
   element parameter 4-5
   equations
      BJTs 16-34 , 16-35 , 16-36 , 16-37
      depletion 15-26
      diffusion 15-26
      diode 15-25
      metal and poly 15-27
      MOSFETs 20-46
   GMIN 16-2
   GMINDC 16-2
   input-output ratio 14-2
   JFETs 17-6
   JFETs and MESFETs 17-6 , 17-25 - 17-30
      CAPOP=2 parameters 17-29
      equations 17-6
      gate to drain 17-5
      source to gate 17-5
   junction, internal collector 16-37
   manufacturing variations 13-24
   matrixes C-52
   model 14-9
      parameters 14-9 , 20-27 - 20-28 , 20-69
      selection 20-57
   MOSFETs
      AC gate 20-97
      BSIM model 21-117
      diodes 20-46
         equations 20-106
      equations 20-74 - 20-98
      gate capacitance 20-66
         example 20-64
         length/width 20-97
         models 20-57
         SPICE Meyer 20-74
      Meyer model 20-57 , 20-71
      models 20-57
   multiconductor C-32
   overlap 20-73
   parameters 14-9
      BJTs 16-11
      junction 15-12
      Meyer 20-71
      MOSFETs
         Cypress 21-169
         IDS LEVEL 5 21-36
         LEVEL 38 21-169
         LEVEL 49 and 53 22-39
         LEVEL 5 21-36
         LEVEL 57 22-124
   parasitic 14-2 , 16-12
   pins 24-6
   plotting 20-66
   scale factor, setting 9-35 , 10-31
   substrate 16-38
   table of values 9-28 , 10-22
   temperature 14-11
      equations 14-11
         BJTs 16-46
   voltage variable 26-84
   wire, equations 14-6
capacitance-voltage plots, generating 9-28 , 10-23
capacitor
   BJT 16-6
   conductance requirement 10-47
   current flow 8-23
   DC sweep evaluation 16-34
   device
      equations 14-10
      model 14-9
   element 4-4 , 14-9
      template listings 8-55
   equation selector option 15-5
   equations 17-6
   models 3-30
      gate 20-57
      list 20-7
      name 4-5
      SPICE 17-5
   parameters
      junction 16-11
      metal and poly 15-13
   switched 29-48
   temperature, equations 14-8
   transcapacitance 20-59
   voltage controlled 5-35 , 5-40
CAPL model parameter C-36
CAPOP model parameter 11-27 , 17-3 , 20-7 , 20-57 , 20-69
   XPART 20-72
   XQC 20-72
CAPTAB option 9-28 , 10-22
cascoding, example 20-55
CASMOS
   GEC model 20-5
   GTE model 20-5
   Rutherford model 20-6
CBD model parameter 20-27
CBS model parameter 20-27
CCCS
   element parameter 26-28
   syntax 5-46
CCVS 5-42
   element parameter 26-23
   syntax 5-42
CDB model parameter 20-28
cell characterization 13-2 , 24-9
CENDIF optimization parameter 13-41
CEXT model parameter C-15 , C-24 , C-26 , C-28
channel length modulation, MOSFETs
   equations
      LEVEL 2 21-15
      LEVEL 3 21-26
      LEVEL 38 21-175
      LEVEL 5 21-48
      LEVEL 6 21-80
      LEVEL 8 21-98
   parameters
      LEVEL 6 21-80
      LEVEL 8 21-93
characteristic impedance C-73
characterization of models 10-14
charge conservation 20-91
   capacitance 20-87
charge tolerance, setting 9-39 , 11-16
CHGTOL option 9-39 , 11-16 , 11-34
circles, defining 18-39
circuits
   adder 31-3
   BiCMOS 16-2
   BJT 16-20 , 16-21
   design
      nonplanar and planar technologies 20-15
      wave processes 20-15
   ECL 16-2
   inverter, MOS 2-7
   model 29-43
      AC analysis 29-47
      transient responses 29-46
   nonconvergent 10-51
   RC
      line 29-33
      network 2-2
   reusable